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[/] [openmsp430/] [trunk/] [fpga/] [OBSOLETE/] [altera_de1_board] - Rev 221

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221 Move old Altera-DE1 project to the OBSOLETE directory.
Create new Altera-DE0-Nano-SoC project, also containing a small demo of the openGFX430 graphic controller.		 olivier.girard 2869d 17h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board
212 Update all FPGA project examples to support both MSPGCC and TI/RedHat GCC toolchains. olivier.girard 3144d 04h /openmsp430/trunk/fpga/altera_de1_board
205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).		 olivier.girard 3268d 18h /openmsp430/trunk/fpga/altera_de1_board
204 Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). olivier.girard 3275d 18h /openmsp430/trunk/fpga/altera_de1_board
202 Add DMA interface support + LINT cleanup olivier.girard 3282d 18h /openmsp430/trunk/fpga/altera_de1_board
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3443d 17h /openmsp430/trunk/fpga/altera_de1_board
193 Update FPGA projects with latest core RTL changes. olivier.girard 3843d 19h /openmsp430/trunk/fpga/altera_de1_board
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3983d 19h /openmsp430/trunk/fpga/altera_de1_board
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 3995d 18h /openmsp430/trunk/fpga/altera_de1_board
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4096d 19h /openmsp430/trunk/fpga/altera_de1_board
185 Update Altera FPGA example bitstream (no functional change... only generated with a newer Quartus version) olivier.girard 4097d 19h /openmsp430/trunk/fpga/altera_de1_board
184 Fixed some project settings for newer Quartus version (12.1) olivier.girard 4097d 19h /openmsp430/trunk/fpga/altera_de1_board
181 Update with latest oMSP Core version. olivier.girard 4138d 18h /openmsp430/trunk/fpga/altera_de1_board
178 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4147d 17h /openmsp430/trunk/fpga/altera_de1_board
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4164d 18h /openmsp430/trunk/fpga/altera_de1_board
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4271d 17h /openmsp430/trunk/fpga/altera_de1_board
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4356d 17h /openmsp430/trunk/fpga/altera_de1_board
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4359d 19h /openmsp430/trunk/fpga/altera_de1_board
143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4430d 19h /openmsp430/trunk/fpga/altera_de1_board
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4447d 04h /openmsp430/trunk/fpga/altera_de1_board
136 Update all FPGA projects with the latest core version. olivier.girard 4478d 18h /openmsp430/trunk/fpga/altera_de1_board
132 Update FPGA examples with the POP.B bug fix olivier.girard 4491d 18h /openmsp430/trunk/fpga/altera_de1_board
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4575d 18h /openmsp430/trunk/fpga/altera_de1_board
112 Modified comment. olivier.girard 4784d 18h /openmsp430/trunk/fpga/altera_de1_board
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4785d 18h /openmsp430/trunk/fpga/altera_de1_board
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4841d 16h /openmsp430/trunk/fpga/altera_de1_board
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4856d 18h /openmsp430/trunk/fpga/altera_de1_board
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4860d 19h /openmsp430/trunk/fpga/altera_de1_board
100 Update HTML documentation with Actel's FPGA implementation example (file & directory description section). olivier.girard 4865d 18h /openmsp430/trunk/fpga/altera_de1_board
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4866d 19h /openmsp430/trunk/fpga/altera_de1_board

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