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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog] - Rev 205

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205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).		 olivier.girard 3280d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
204 Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). olivier.girard 3287d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
202 Add DMA interface support + LINT cleanup olivier.girard 3294d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3455d 10h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
193 Update FPGA projects with latest core RTL changes. olivier.girard 3855d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3995d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 4007d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4108d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
181 Update with latest oMSP Core version. olivier.girard 4150d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4176d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4283d 10h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4368d 10h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4371d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
136 Update all FPGA projects with the latest core version. olivier.girard 4490d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
132 Update FPGA examples with the POP.B bug fix olivier.girard 4503d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4587d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
112 Modified comment. olivier.girard 4796d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4797d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4853d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4868d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4872d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4886d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4909d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
85 Diverse RTL cosmetic updates. olivier.girard 4909d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4914d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
82 Update Actel example project:
- synthesis scripts.
- Spacewar demo program.
- SVN ignore patterns for diverse directories		 olivier.girard 4960d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
81 Initial synthesis, P&R setup for the Actel example project. olivier.girard 4963d 10h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4963d 19h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog

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