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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] - Rev 205

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205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).		 olivier.girard 3352d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
204 Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). olivier.girard 3359d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
202 Add DMA interface support + LINT cleanup olivier.girard 3366d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3527d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
197 Fixed bug on the write strobe of the baudrate hi configuration register. olivier.girard 3884d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
193 Update FPGA projects with latest core RTL changes. olivier.girard 3927d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 4067d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 4079d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4180d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
181 Update with latest oMSP Core version. olivier.girard 4222d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4248d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4355d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4440d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4443d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
136 Update all FPGA projects with the latest core version. olivier.girard 4562d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
132 Update FPGA examples with the POP.B bug fix olivier.girard 4575d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4659d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
112 Modified comment. olivier.girard 4868d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4869d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4923d 17h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4940d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4944d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4958d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4981d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
85 Diverse RTL cosmetic updates. olivier.girard 4981d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4986d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 5047d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5134d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
72 Expand configurability options of the program and data memory sizes. olivier.girard 5161d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5308d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl

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