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208 Update tools to run with latest CPU core version. olivier.girard 3147d 20h /openmsp430/
207 Simulation now works seamlessly under Linux, OS-X and Windows (Cygwin) olivier.girard 3147d 20h /openmsp430/
206 Update ChangeLog olivier.girard 3244d 20h /openmsp430/
205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).		 olivier.girard 3244d 20h /openmsp430/
204 Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). olivier.girard 3251d 21h /openmsp430/
203 Update ChangeLog olivier.girard 3258d 20h /openmsp430/
202 Add DMA interface support + LINT cleanup olivier.girard 3258d 20h /openmsp430/
201 Update ChangeLog olivier.girard 3419d 19h /openmsp430/
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3419d 19h /openmsp430/
199 Update ChangeLog olivier.girard 3525d 22h /openmsp430/
198 Update GDB-Proxy to support new GCC/GDB compiler version from RedHat/TI olivier.girard 3525d 22h /openmsp430/
197 Fixed bug on the write strobe of the baudrate hi configuration register. olivier.girard 3776d 21h /openmsp430/
196 Update ChangeLog olivier.girard 3819d 20h /openmsp430/
195 Update HTML documentation with configurable number of IRQ option. olivier.girard 3819d 20h /openmsp430/
194 Update PDF and ODT documentation. olivier.girard 3819d 21h /openmsp430/
193 Update FPGA projects with latest core RTL changes. olivier.girard 3819d 21h /openmsp430/
192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 3819d 21h /openmsp430/
191 Update ChangeLog olivier.girard 3959d 21h /openmsp430/
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3959d 21h /openmsp430/
189 Update ChangeLog olivier.girard 3971d 21h /openmsp430/
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 3971d 21h /openmsp430/
187 Update ChangeLog olivier.girard 4072d 21h /openmsp430/
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4072d 21h /openmsp430/
185 Update Altera FPGA example bitstream (no functional change... only generated with a newer Quartus version) olivier.girard 4073d 21h /openmsp430/
184 Fixed some project settings for newer Quartus version (12.1) olivier.girard 4073d 21h /openmsp430/
183 Update ChangeLog olivier.girard 4114d 20h /openmsp430/
182 Minor update to reflect new ASIC_CLOCKING option. olivier.girard 4114d 20h /openmsp430/
181 Update with latest oMSP Core version. olivier.girard 4114d 20h /openmsp430/
180 Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-)		 olivier.girard 4114d 20h /openmsp430/
179 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4123d 19h /openmsp430/

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