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210 Add support for both MSPGCC and TI/RH-GCC toolchains. Add detection of debug ports for OS-X. olivier.girard 3125d 21h /openmsp430/trunk/
209 Update ChangeLogs olivier.girard 3153d 10h /openmsp430/trunk/
208 Update tools to run with latest CPU core version. olivier.girard 3153d 10h /openmsp430/trunk/
207 Simulation now works seamlessly under Linux, OS-X and Windows (Cygwin) olivier.girard 3153d 10h /openmsp430/trunk/
206 Update ChangeLog olivier.girard 3250d 10h /openmsp430/trunk/
205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).		 olivier.girard 3250d 10h /openmsp430/trunk/
204 Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). olivier.girard 3257d 10h /openmsp430/trunk/
203 Update ChangeLog olivier.girard 3264d 09h /openmsp430/trunk/
202 Add DMA interface support + LINT cleanup olivier.girard 3264d 09h /openmsp430/trunk/
201 Update ChangeLog olivier.girard 3425d 09h /openmsp430/trunk/
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3425d 09h /openmsp430/trunk/
199 Update ChangeLog olivier.girard 3531d 11h /openmsp430/trunk/
198 Update GDB-Proxy to support new GCC/GDB compiler version from RedHat/TI olivier.girard 3531d 11h /openmsp430/trunk/
197 Fixed bug on the write strobe of the baudrate hi configuration register. olivier.girard 3782d 10h /openmsp430/trunk/
196 Update ChangeLog olivier.girard 3825d 09h /openmsp430/trunk/
195 Update HTML documentation with configurable number of IRQ option. olivier.girard 3825d 09h /openmsp430/trunk/
194 Update PDF and ODT documentation. olivier.girard 3825d 10h /openmsp430/trunk/
193 Update FPGA projects with latest core RTL changes. olivier.girard 3825d 10h /openmsp430/trunk/
192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 3825d 10h /openmsp430/trunk/
191 Update ChangeLog olivier.girard 3965d 10h /openmsp430/trunk/
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3965d 10h /openmsp430/trunk/
189 Update ChangeLog olivier.girard 3977d 10h /openmsp430/trunk/
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 3977d 10h /openmsp430/trunk/
187 Update ChangeLog olivier.girard 4078d 11h /openmsp430/trunk/
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4078d 11h /openmsp430/trunk/
185 Update Altera FPGA example bitstream (no functional change... only generated with a newer Quartus version) olivier.girard 4079d 11h /openmsp430/trunk/
184 Fixed some project settings for newer Quartus version (12.1) olivier.girard 4079d 11h /openmsp430/trunk/
183 Update ChangeLog olivier.girard 4120d 09h /openmsp430/trunk/
182 Minor update to reflect new ASIC_CLOCKING option. olivier.girard 4120d 09h /openmsp430/trunk/
181 Update with latest oMSP Core version. olivier.girard 4120d 09h /openmsp430/trunk/

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