| Rev |
Log message |
Author |
Age |
Path |
| 204 |
Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). |
olivier.girard |
3258d 23h |
/openmsp430/trunk/core/rtl/ |
| 202 |
Add DMA interface support + LINT cleanup |
olivier.girard |
3265d 23h |
/openmsp430/trunk/core/rtl/ |
| 200 |
Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. |
olivier.girard |
3426d 22h |
/openmsp430/trunk/core/rtl/ |
| 192 |
Number of supported IRQs is now configurable to 14 (default), 30 or 62. |
olivier.girard |
3827d 00h |
/openmsp430/trunk/core/rtl/ |
| 190 |
Remove dummy memory read access for CMP and BIT instructions. |
olivier.girard |
3967d 00h |
/openmsp430/trunk/core/rtl/ |
| 188 |
Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. |
olivier.girard |
3978d 23h |
/openmsp430/trunk/core/rtl/ |
| 186 |
Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 |
olivier.girard |
4080d 00h |
/openmsp430/trunk/core/rtl/ |
| 180 |
Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-) |
olivier.girard |
4121d 22h |
/openmsp430/trunk/core/rtl/ |
| 175 |
Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports. |
olivier.girard |
4147d 22h |
/openmsp430/trunk/core/rtl/ |
| 174 |
Cleanup dmem_wr generation logic. Important note: this is not a bug fix, only beautification. |
olivier.girard |
4147d 23h |
/openmsp430/trunk/core/rtl/ |
| 154 |
The serial debug interface now supports the I2C protocol (in addition to the UART) |
olivier.girard |
4254d 23h |
/openmsp430/trunk/core/rtl/ |
| 151 |
Add possibility to configure custom Program, Data and Peripheral memory sizes. |
olivier.girard |
4339d 21h |
/openmsp430/trunk/core/rtl/ |
| 149 |
Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface) |
olivier.girard |
4343d 00h |
/openmsp430/trunk/core/rtl/ |
| 134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4461d 23h |
/openmsp430/trunk/core/rtl/ |
| 132 |
Update FPGA examples with the POP.B bug fix |
olivier.girard |
4474d 23h |
/openmsp430/trunk/core/rtl/ |
| 130 |
Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) |
olivier.girard |
4482d 22h |
/openmsp430/trunk/core/rtl/ |
| 128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4558d 23h |
/openmsp430/trunk/core/rtl/ |
| 117 |
To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. |
olivier.girard |
4735d 00h |
/openmsp430/trunk/core/rtl/ |
| 112 |
Modified comment. |
olivier.girard |
4767d 23h |
/openmsp430/trunk/core/rtl/ |
| 111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4768d 23h |
/openmsp430/trunk/core/rtl/ |
| 106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4824d 22h |
/openmsp430/trunk/core/rtl/ |
| 105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
4839d 23h |
/openmsp430/trunk/core/rtl/ |
| 103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4845d 05h |
/openmsp430/trunk/core/rtl/ |
| 102 |
Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:
- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+ |
olivier.girard |
4845d 22h |
/openmsp430/trunk/core/rtl/ |
| 101 |
Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. |
olivier.girard |
4846d 00h |
/openmsp430/trunk/core/rtl/ |
| 91 |
Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface. |
olivier.girard |
4858d 00h |
/openmsp430/trunk/core/rtl/ |
| 86 |
Update serial debug interface test patterns to make them work with all program memory configurations. |
olivier.girard |
4880d 21h |
/openmsp430/trunk/core/rtl/ |
| 85 |
Diverse RTL cosmetic updates. |
olivier.girard |
4880d 23h |
/openmsp430/trunk/core/rtl/ |
| 84 |
Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface. |
olivier.girard |
4886d 00h |
/openmsp430/trunk/core/rtl/ |
| 79 |
Update the GPIO peripheral to fix a potential synchronization issue. |
olivier.girard |
4947d 00h |
/openmsp430/trunk/core/rtl/ |
