Rev |
Log message |
Author |
Age |
Path |
192 |
Number of supported IRQs is now configurable to 14 (default), 30 or 62. |
olivier.girard |
3844d 11h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
186 |
Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 |
olivier.girard |
4097d 11h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
180 |
Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-) |
olivier.girard |
4139d 10h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
178 |
Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-) |
olivier.girard |
4148d 09h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
175 |
Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports. |
olivier.girard |
4165d 10h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
154 |
The serial debug interface now supports the I2C protocol (in addition to the UART) |
olivier.girard |
4272d 10h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
151 |
Add possibility to configure custom Program, Data and Peripheral memory sizes. |
olivier.girard |
4357d 09h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
149 |
Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface) |
olivier.girard |
4360d 11h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
145 |
Add Dhrystone and CoreMark benchmarks to the simulation environment. |
olivier.girard |
4410d 10h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
142 |
Beautify the linker script examples. |
olivier.girard |
4431d 11h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
141 |
Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) |
olivier.girard |
4435d 10h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4479d 10h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4576d 10h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
115 |
Add linker script example. |
olivier.girard |
4777d 11h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4786d 10h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4842d 09h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
4857d 10h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4862d 16h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
102 |
Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:
- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+ |
olivier.girard |
4863d 09h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
101 |
Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. |
olivier.girard |
4863d 11h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
95 |
Update some test patterns for the additional simulator supports. |
olivier.girard |
4871d 10h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
91 |
Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface. |
olivier.girard |
4875d 11h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
86 |
Update serial debug interface test patterns to make them work with all program memory configurations. |
olivier.girard |
4898d 08h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
85 |
Diverse RTL cosmetic updates. |
olivier.girard |
4898d 10h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
79 |
Update the GPIO peripheral to fix a potential synchronization issue. |
olivier.girard |
4964d 11h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
74 |
Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly. |
olivier.girard |
5051d 11h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
67 |
Added 16x16 Hardware Multiplier. |
olivier.girard |
5225d 19h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
58 |
Update the debug hardware breakpoint verification patterns to reflect the latest design updates. |
olivier.girard |
5259d 08h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
55 |
Add a "sandbox" test pattern to play around with the simulation :-P |
olivier.girard |
5264d 10h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
34 |
To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. |
olivier.girard |
5293d 12h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |