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[/] [openmsp430/] [trunk/] [fpga/] - Rev 191

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Rev Log message Author Age Path
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3982d 02h /openmsp430/trunk/fpga/
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 3994d 02h /openmsp430/trunk/fpga/
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4095d 02h /openmsp430/trunk/fpga/
185 Update Altera FPGA example bitstream (no functional change... only generated with a newer Quartus version) olivier.girard 4096d 03h /openmsp430/trunk/fpga/
184 Fixed some project settings for newer Quartus version (12.1) olivier.girard 4096d 03h /openmsp430/trunk/fpga/
181 Update with latest oMSP Core version. olivier.girard 4137d 01h /openmsp430/trunk/fpga/
179 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4146d 01h /openmsp430/trunk/fpga/
178 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4146d 01h /openmsp430/trunk/fpga/
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4163d 01h /openmsp430/trunk/fpga/
171 Update in order to add Hardware breakpoint support.
Hardware breakpoint are here only added for development purpose in order to add multi-core features as well as software & hardware breakpoint support to the GDB-Proxy.		 olivier.girard 4196d 23h /openmsp430/trunk/fpga/
168 Add missing second oMSP system. olivier.girard 4218d 01h /openmsp430/trunk/fpga/
167 Update LX9 Microboard FPGA example.
It now includes a dual-core oMSP system with a shared 16kB program memory.
Each core has its own 2kB data memory and an additional 2kB shared data memory.		 olivier.girard 4218d 01h /openmsp430/trunk/fpga/
165 Add missing I2C address in the README file. olivier.girard 4232d 02h /openmsp430/trunk/fpga/
162 Add some more SVN ignore patterns.
Update testbench.		 olivier.girard 4270d 00h /openmsp430/trunk/fpga/
161 add some SVN ignore patterns olivier.girard 4270d 01h /openmsp430/trunk/fpga/
157 Re-create new LX9 Microboard project to show off the new I2C serial debug interface (and more to come).... olivier.girard 4270d 01h /openmsp430/trunk/fpga/
156 Remove current LX9 microboard project (to be replaced with a new one showing off the new I2C based serial debug interface) olivier.girard 4270d 01h /openmsp430/trunk/fpga/
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4270d 01h /openmsp430/trunk/fpga/
153 Update XFLOW scripts to bring more automation.
Several bitstreams are now checked in for direct use.		 olivier.girard 4325d 00h /openmsp430/trunk/fpga/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4355d 00h /openmsp430/trunk/fpga/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4358d 02h /openmsp430/trunk/fpga/
143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4429d 02h /openmsp430/trunk/fpga/
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4445d 11h /openmsp430/trunk/fpga/
136 Update all FPGA projects with the latest core version. olivier.girard 4477d 01h /openmsp430/trunk/fpga/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4490d 02h /openmsp430/trunk/fpga/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4574d 01h /openmsp430/trunk/fpga/
121 Add a new FPGA example for the LX9 Microboard from Avnet.
Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)		 olivier.girard 4718d 02h /openmsp430/trunk/fpga/
112 Modified comment. olivier.girard 4783d 02h /openmsp430/trunk/fpga/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4784d 02h /openmsp430/trunk/fpga/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4838d 11h /openmsp430/trunk/fpga/

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