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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] - Rev 226

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212 Update all FPGA project examples to support both MSPGCC and TI/RedHat GCC toolchains. olivier.girard 3163d 19h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).		 olivier.girard 3288d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
204 Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). olivier.girard 3295d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
202 Add DMA interface support + LINT cleanup olivier.girard 3302d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3463d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
193 Update FPGA projects with latest core RTL changes. olivier.girard 3863d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 4003d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 4015d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4116d 10h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
181 Update with latest oMSP Core version. olivier.girard 4158d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
178 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4167d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4184d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4291d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4376d 07h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4379d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4450d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4466d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
136 Update all FPGA projects with the latest core version. olivier.girard 4498d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4511d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4595d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
112 Modified comment. olivier.girard 4804d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4805d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4861d 07h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4861d 07h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4876d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4880d 10h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4886d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4890d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4894d 10h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4917d 07h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/

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