| Rev |
Log message |
Author |
Age |
Path |
| 197 |
Fixed bug on the write strobe of the baudrate hi configuration register. |
olivier.girard |
3815d 16h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 193 |
Update FPGA projects with latest core RTL changes. |
olivier.girard |
3858d 16h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 190 |
Remove dummy memory read access for CMP and BIT instructions. |
olivier.girard |
3998d 16h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 188 |
Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. |
olivier.girard |
4010d 16h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 186 |
Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 |
olivier.girard |
4111d 16h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 181 |
Update with latest oMSP Core version. |
olivier.girard |
4153d 15h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 179 |
Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-) |
olivier.girard |
4162d 15h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 176 |
Update FPGA projects with latest openMSP430 core RTL |
olivier.girard |
4179d 15h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 155 |
Update FPGA projects with the latest openMSP430 verilog code. |
olivier.girard |
4286d 15h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 153 |
Update XFLOW scripts to bring more automation.
Several bitstreams are now checked in for direct use. |
olivier.girard |
4341d 14h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 151 |
Add possibility to configure custom Program, Data and Peripheral memory sizes. |
olivier.girard |
4371d 14h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 149 |
Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface) |
olivier.girard |
4374d 16h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 143 |
Update FPGA software examples to support MSPGCC Uniarch. |
olivier.girard |
4445d 16h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 138 |
Update simulation scripts to support Cygwin out of the box for Windows users. |
olivier.girard |
4462d 01h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 136 |
Update all FPGA projects with the latest core version. |
olivier.girard |
4493d 15h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 132 |
Update FPGA examples with the POP.B bug fix |
olivier.girard |
4506d 16h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4590d 15h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 112 |
Modified comment. |
olivier.girard |
4799d 16h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4800d 16h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 109 |
Update Xilinx FPGA example with the latest openMSP430 core RTL version. |
olivier.girard |
4855d 00h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4856d 14h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
4871d 15h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 104 |
Update all FPGA example projects with the latest RTL version. |
olivier.girard |
4875d 16h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 98 |
Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated. |
olivier.girard |
4881d 16h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 94 |
Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim |
olivier.girard |
4885d 16h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 91 |
Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface. |
olivier.girard |
4889d 17h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 86 |
Update serial debug interface test patterns to make them work with all program memory configurations. |
olivier.girard |
4912d 13h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 85 |
Diverse RTL cosmetic updates. |
olivier.girard |
4912d 15h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 84 |
Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface. |
olivier.girard |
4917d 16h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 79 |
Update the GPIO peripheral to fix a potential synchronization issue. |
olivier.girard |
4978d 17h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
