| Rev |
Log message |
Author |
Age |
Path |
| 212 |
Update all FPGA project examples to support both MSPGCC and TI/RedHat GCC toolchains. |
olivier.girard |
3127d 11h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 205 |
Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools). |
olivier.girard |
3252d 01h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 204 |
Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). |
olivier.girard |
3259d 02h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 202 |
Add DMA interface support + LINT cleanup |
olivier.girard |
3266d 01h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 200 |
Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. |
olivier.girard |
3427d 00h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 197 |
Fixed bug on the write strobe of the baudrate hi configuration register. |
olivier.girard |
3784d 02h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 193 |
Update FPGA projects with latest core RTL changes. |
olivier.girard |
3827d 02h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 190 |
Remove dummy memory read access for CMP and BIT instructions. |
olivier.girard |
3967d 02h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 188 |
Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. |
olivier.girard |
3979d 02h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 186 |
Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 |
olivier.girard |
4080d 02h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 181 |
Update with latest oMSP Core version. |
olivier.girard |
4122d 01h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 179 |
Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-) |
olivier.girard |
4131d 00h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 176 |
Update FPGA projects with latest openMSP430 core RTL |
olivier.girard |
4148d 01h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 155 |
Update FPGA projects with the latest openMSP430 verilog code. |
olivier.girard |
4255d 01h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 153 |
Update XFLOW scripts to bring more automation.
Several bitstreams are now checked in for direct use. |
olivier.girard |
4310d 00h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 151 |
Add possibility to configure custom Program, Data and Peripheral memory sizes. |
olivier.girard |
4340d 00h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 149 |
Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface) |
olivier.girard |
4343d 02h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 143 |
Update FPGA software examples to support MSPGCC Uniarch. |
olivier.girard |
4414d 02h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 138 |
Update simulation scripts to support Cygwin out of the box for Windows users. |
olivier.girard |
4430d 11h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 136 |
Update all FPGA projects with the latest core version. |
olivier.girard |
4462d 01h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 132 |
Update FPGA examples with the POP.B bug fix |
olivier.girard |
4475d 01h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4559d 01h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 112 |
Modified comment. |
olivier.girard |
4768d 01h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4769d 01h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 109 |
Update Xilinx FPGA example with the latest openMSP430 core RTL version. |
olivier.girard |
4823d 10h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4825d 00h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
4840d 01h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 104 |
Update all FPGA example projects with the latest RTL version. |
olivier.girard |
4844d 02h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 98 |
Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated. |
olivier.girard |
4850d 02h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
| 94 |
Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim |
olivier.girard |
4854d 02h |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/ |
