OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] - Rev 186

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4138d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
181 Update with latest oMSP Core version. olivier.girard 4180d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4206d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4313d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4398d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4401d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
136 Update all FPGA projects with the latest core version. olivier.girard 4520d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4533d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4617d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
112 Modified comment. olivier.girard 4826d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4827d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4881d 17h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4898d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4902d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4916d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4939d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
85 Diverse RTL cosmetic updates. olivier.girard 4939d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4944d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 5005d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5092d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5119d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5266d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
61 Update openMSP430 rtl. olivier.girard 5298d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
59 Update the FPGA projects with the latest core design updates. olivier.girard 5300d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5305d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
37 olivier.girard 5334d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
36 Remove old core version. olivier.girard 5334d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5344d 16h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5344d 17h /openmsp430/trunk/fpga/diligent_s3board/rtl/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5455d 13h /openmsp430/trunk/fpga/diligent_s3board/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.