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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] - Rev 197

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Rev Log message Author Age Path
197 Fixed bug on the write strobe of the baudrate hi configuration register. olivier.girard 3821d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
193 Update FPGA projects with latest core RTL changes. olivier.girard 3864d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 4004d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 4016d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4117d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
181 Update with latest oMSP Core version. olivier.girard 4159d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4185d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4292d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4377d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4380d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
136 Update all FPGA projects with the latest core version. olivier.girard 4499d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4512d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4596d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
112 Modified comment. olivier.girard 4805d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4806d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4860d 16h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4877d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4881d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4895d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4918d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
85 Diverse RTL cosmetic updates. olivier.girard 4918d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4923d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4984d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5071d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5098d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5245d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
61 Update openMSP430 rtl. olivier.girard 5277d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
59 Update the FPGA projects with the latest core design updates. olivier.girard 5279d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5284d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
37 olivier.girard 5313d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/

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