OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] - Rev 192

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 3822d 21h /
191 Update ChangeLog olivier.girard 3962d 20h /
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3962d 20h /
189 Update ChangeLog olivier.girard 3974d 20h /
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 3974d 20h /
187 Update ChangeLog olivier.girard 4075d 21h /
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4075d 21h /
185 Update Altera FPGA example bitstream (no functional change... only generated with a newer Quartus version) olivier.girard 4076d 21h /
184 Fixed some project settings for newer Quartus version (12.1) olivier.girard 4076d 21h /
183 Update ChangeLog olivier.girard 4117d 19h /
182 Minor update to reflect new ASIC_CLOCKING option. olivier.girard 4117d 19h /
181 Update with latest oMSP Core version. olivier.girard 4117d 19h /
180 Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-)		 olivier.girard 4117d 19h /
179 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4126d 19h /
178 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4126d 19h /
177 Update ChangeLog olivier.girard 4143d 19h /
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4143d 19h /
175 Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports.		 olivier.girard 4143d 19h /
174 Cleanup dmem_wr generation logic. Important note: this is not a bug fix, only beautification. olivier.girard 4143d 20h /
173 Update ChangeLog olivier.girard 4177d 18h /
172 GDB-Proxy now supports multi-core systems as well as hardware and software memory breakpoints.
It is to be noted that in a multi-core environment, software breakpoints can be configured for shared or dedicated program memory topologies.		 olivier.girard 4177d 18h /
171 Update in order to add Hardware breakpoint support.
Hardware breakpoint are here only added for development purpose in order to add multi-core features as well as software & hardware breakpoint support to the GDB-Proxy.		 olivier.girard 4177d 18h /
170 Update ChangeLog olivier.girard 4198d 20h /
169 Update the Mini-debugger with multi-core support.
Up to quad core systems are now supported by the GUI.		 olivier.girard 4198d 20h /
168 Add missing second oMSP system. olivier.girard 4198d 20h /
167 Update LX9 Microboard FPGA example.
It now includes a dual-core oMSP system with a shared 16kB program memory.
Each core has its own 2kB data memory and an additional 2kB shared data memory.		 olivier.girard 4198d 20h /
166 Update documentation with new I2C based serial debug interface olivier.girard 4207d 19h /
165 Add missing I2C address in the README file. olivier.girard 4212d 20h /
164 Update ChangeLog olivier.girard 4239d 19h /
163 Fixed font handling problem olivier.girard 4239d 19h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.