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193 Update FPGA projects with latest core RTL changes. olivier.girard 3834d 19h /openmsp430/
192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 3834d 19h /openmsp430/
191 Update ChangeLog olivier.girard 3974d 19h /openmsp430/
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3974d 19h /openmsp430/
189 Update ChangeLog olivier.girard 3986d 19h /openmsp430/
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 3986d 19h /openmsp430/
187 Update ChangeLog olivier.girard 4087d 20h /openmsp430/
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4087d 20h /openmsp430/
185 Update Altera FPGA example bitstream (no functional change... only generated with a newer Quartus version) olivier.girard 4088d 20h /openmsp430/
184 Fixed some project settings for newer Quartus version (12.1) olivier.girard 4088d 20h /openmsp430/

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