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[/] [openmsp430/] - Rev 192

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192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 3843d 09h /openmsp430
191 Update ChangeLog olivier.girard 3983d 09h /openmsp430
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3983d 09h /openmsp430
189 Update ChangeLog olivier.girard 3995d 09h /openmsp430
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 3995d 09h /openmsp430
187 Update ChangeLog olivier.girard 4096d 09h /openmsp430
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4096d 09h /openmsp430
185 Update Altera FPGA example bitstream (no functional change... only generated with a newer Quartus version) olivier.girard 4097d 09h /openmsp430
184 Fixed some project settings for newer Quartus version (12.1) olivier.girard 4097d 10h /openmsp430
183 Update ChangeLog olivier.girard 4138d 08h /openmsp430
182 Minor update to reflect new ASIC_CLOCKING option. olivier.girard 4138d 08h /openmsp430
181 Update with latest oMSP Core version. olivier.girard 4138d 08h /openmsp430
180 Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-)		 olivier.girard 4138d 08h /openmsp430
179 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4147d 08h /openmsp430
178 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4147d 08h /openmsp430
177 Update ChangeLog olivier.girard 4164d 08h /openmsp430
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4164d 08h /openmsp430
175 Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports.		 olivier.girard 4164d 08h /openmsp430
174 Cleanup dmem_wr generation logic. Important note: this is not a bug fix, only beautification. olivier.girard 4164d 08h /openmsp430
173 Update ChangeLog olivier.girard 4198d 06h /openmsp430

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