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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] - Rev 202

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202 Add DMA interface support + LINT cleanup olivier.girard 3289d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3450d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
193 Update FPGA projects with latest core RTL changes. olivier.girard 3850d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3990d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 4002d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4103d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
181 Update with latest oMSP Core version. olivier.girard 4145d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4171d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4278d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4363d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4366d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
136 Update all FPGA projects with the latest core version. olivier.girard 4485d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
132 Update FPGA examples with the POP.B bug fix olivier.girard 4498d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4582d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
112 Modified comment. olivier.girard 4791d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4792d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4848d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4863d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4867d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4881d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl

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