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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] - Rev 199

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197 Fixed bug on the write strobe of the baudrate hi configuration register. olivier.girard 3851d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board
193 Update FPGA projects with latest core RTL changes. olivier.girard 3894d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 4034d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 4046d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4147d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board
181 Update with latest oMSP Core version. olivier.girard 4189d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board
179 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4198d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4215d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4322d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board
153 Update XFLOW scripts to bring more automation.
Several bitstreams are now checked in for direct use.		 olivier.girard 4377d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4407d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4410d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board
143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4481d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4497d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board
136 Update all FPGA projects with the latest core version. olivier.girard 4529d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board
132 Update FPGA examples with the POP.B bug fix olivier.girard 4542d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4626d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board
112 Modified comment. olivier.girard 4835d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4836d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4890d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board

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