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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] - Rev 193

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193 Update FPGA projects with latest core RTL changes. olivier.girard 3864d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 4004d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 4016d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4117d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
181 Update with latest oMSP Core version. olivier.girard 4159d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4185d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4292d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4377d 03h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4380d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
136 Update all FPGA projects with the latest core version. olivier.girard 4499d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
132 Update FPGA examples with the POP.B bug fix olivier.girard 4512d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4596d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
112 Modified comment. olivier.girard 4805d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4806d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4860d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4877d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4881d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4895d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4918d 03h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
85 Diverse RTL cosmetic updates. olivier.girard 4918d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430

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