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Rev	Log message	Author	Age	Path
191	Update ChangeLog	olivier.girard	4004d 12h	/
190	Remove dummy memory read access for CMP and BIT instructions.	olivier.girard	4004d 12h	/
189	Update ChangeLog	olivier.girard	4016d 12h	/
188	Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c.	olivier.girard	4016d 12h	/
187	Update ChangeLog	olivier.girard	4117d 12h	/
186	Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247	olivier.girard	4117d 12h	/
185	Update Altera FPGA example bitstream (no functional change... only generated with a newer Quartus version)	olivier.girard	4118d 13h	/
184	Fixed some project settings for newer Quartus version (12.1)	olivier.girard	4118d 13h	/
183	Update ChangeLog	olivier.girard	4159d 11h	/
182	Minor update to reflect new ASIC_CLOCKING option.	olivier.girard	4159d 11h	/
181	Update with latest oMSP Core version.	olivier.girard	4159d 11h	/
180	Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme. Thanks to Sebastien Van Cauwenberghe's contribution :-)	olivier.girard	4159d 11h	/
179	Update all linker scripts with a simplified version. Thanks to Mihai M. for this one :-)	olivier.girard	4168d 11h	/
178	Update all linker scripts with a simplified version. Thanks to Mihai M. for this one :-)	olivier.girard	4168d 11h	/
177	Update ChangeLog	olivier.girard	4185d 11h	/
176	Update FPGA projects with latest openMSP430 core RTL	olivier.girard	4185d 11h	/
175	Update hardware breakpoint unit with the followings: - fixed hardware breakpoint bug with CALL instructions. - modified data read watchpoint behavior to also trigger with read/modify/write instructions. - removed unused ports.	olivier.girard	4185d 11h	/
174	Cleanup dmem_wr generation logic. Important note: this is not a bug fix, only beautification.	olivier.girard	4185d 11h	/
173	Update ChangeLog	olivier.girard	4219d 09h	/
172	GDB-Proxy now supports multi-core systems as well as hardware and software memory breakpoints. It is to be noted that in a multi-core environment, software breakpoints can be configured for shared or dedicated program memory topologies.	olivier.girard	4219d 09h	/

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[/] - Rev 191

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