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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] - Rev 200

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200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3452d 01h /openmsp430/trunk/core/sim/rtl_sim
192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 3852d 03h /openmsp430/trunk/core/sim/rtl_sim
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4105d 03h /openmsp430/trunk/core/sim/rtl_sim
180 Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-)
olivier.girard 4147d 02h /openmsp430/trunk/core/sim/rtl_sim
178 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)
olivier.girard 4156d 02h /openmsp430/trunk/core/sim/rtl_sim
175 Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports.
olivier.girard 4173d 02h /openmsp430/trunk/core/sim/rtl_sim
154 The serial debug interface now supports the I2C protocol (in addition to the UART) olivier.girard 4280d 03h /openmsp430/trunk/core/sim/rtl_sim
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4365d 01h /openmsp430/trunk/core/sim/rtl_sim
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)
olivier.girard 4368d 03h /openmsp430/trunk/core/sim/rtl_sim
145 Add Dhrystone and CoreMark benchmarks to the simulation environment. olivier.girard 4418d 02h /openmsp430/trunk/core/sim/rtl_sim
142 Beautify the linker script examples. olivier.girard 4439d 03h /openmsp430/trunk/core/sim/rtl_sim
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 4443d 02h /openmsp430/trunk/core/sim/rtl_sim
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4455d 12h /openmsp430/trunk/core/sim/rtl_sim
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.
olivier.girard 4487d 03h /openmsp430/trunk/core/sim/rtl_sim
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4584d 02h /openmsp430/trunk/core/sim/rtl_sim
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.
olivier.girard 4656d 03h /openmsp430/trunk/core/sim/rtl_sim
115 Add linker script example. olivier.girard 4785d 04h /openmsp430/trunk/core/sim/rtl_sim
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 4794d 03h /openmsp430/trunk/core/sim/rtl_sim
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
olivier.girard 4850d 01h /openmsp430/trunk/core/sim/rtl_sim
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.
olivier.girard 4865d 02h /openmsp430/trunk/core/sim/rtl_sim

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