OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core] - Rev 200

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3455d 13h /openmsp430/trunk/core
192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 3855d 15h /openmsp430/trunk/core
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3995d 15h /openmsp430/trunk/core
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 4007d 14h /openmsp430/trunk/core
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4108d 15h /openmsp430/trunk/core
180 Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-)		 olivier.girard 4150d 14h /openmsp430/trunk/core
178 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4159d 13h /openmsp430/trunk/core
175 Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports.		 olivier.girard 4176d 14h /openmsp430/trunk/core
174 Cleanup dmem_wr generation logic. Important note: this is not a bug fix, only beautification. olivier.girard 4176d 14h /openmsp430/trunk/core
154 The serial debug interface now supports the I2C protocol (in addition to the UART) olivier.girard 4283d 14h /openmsp430/trunk/core
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4368d 13h /openmsp430/trunk/core
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4371d 15h /openmsp430/trunk/core
145 Add Dhrystone and CoreMark benchmarks to the simulation environment. olivier.girard 4421d 14h /openmsp430/trunk/core
142 Beautify the linker script examples. olivier.girard 4442d 15h /openmsp430/trunk/core
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 4446d 14h /openmsp430/trunk/core
139 Add some SVN ignore patterns olivier.girard 4459d 00h /openmsp430/trunk/core
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4459d 00h /openmsp430/trunk/core
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4490d 14h /openmsp430/trunk/core
132 Update FPGA examples with the POP.B bug fix olivier.girard 4503d 14h /openmsp430/trunk/core
130 Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) olivier.girard 4511d 13h /openmsp430/trunk/core

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.