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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit] - Rev 200

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200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3443d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
193 Update FPGA projects with latest core RTL changes. olivier.girard 3843d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3983d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 3995d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4096d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
181 Update with latest oMSP Core version. olivier.girard 4138d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
178 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4147d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4164d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4271d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4356d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4359d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4430d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4447d 01h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
136 Update all FPGA projects with the latest core version. olivier.girard 4478d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
132 Update FPGA examples with the POP.B bug fix olivier.girard 4491d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4575d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
112 Modified comment. olivier.girard 4784d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4785d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4841d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4841d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit

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