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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] - Rev 205

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205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).		 olivier.girard 3324d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
204 Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). olivier.girard 3331d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
202 Add DMA interface support + LINT cleanup olivier.girard 3338d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3499d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
197 Fixed bug on the write strobe of the baudrate hi configuration register. olivier.girard 3856d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
193 Update FPGA projects with latest core RTL changes. olivier.girard 3899d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 4039d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 4051d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4152d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
181 Update with latest oMSP Core version. olivier.girard 4194d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4220d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4327d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4412d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4415d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
136 Update all FPGA projects with the latest core version. olivier.girard 4534d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
132 Update FPGA examples with the POP.B bug fix olivier.girard 4547d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4631d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
112 Modified comment. olivier.girard 4840d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4841d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4895d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog

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