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205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).		 olivier.girard 3399d 17h /
204 Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). olivier.girard 3406d 17h /
203 Update ChangeLog olivier.girard 3413d 16h /
202 Add DMA interface support + LINT cleanup olivier.girard 3413d 16h /
201 Update ChangeLog olivier.girard 3574d 16h /
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3574d 16h /
199 Update ChangeLog olivier.girard 3680d 18h /
198 Update GDB-Proxy to support new GCC/GDB compiler version from RedHat/TI olivier.girard 3680d 18h /
197 Fixed bug on the write strobe of the baudrate hi configuration register. olivier.girard 3931d 17h /
196 Update ChangeLog olivier.girard 3974d 16h /
195 Update HTML documentation with configurable number of IRQ option. olivier.girard 3974d 16h /
194 Update PDF and ODT documentation. olivier.girard 3974d 17h /
193 Update FPGA projects with latest core RTL changes. olivier.girard 3974d 17h /
192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 3974d 17h /
191 Update ChangeLog olivier.girard 4114d 17h /
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 4114d 17h /
189 Update ChangeLog olivier.girard 4126d 17h /
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 4126d 17h /
187 Update ChangeLog olivier.girard 4227d 18h /
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4227d 18h /

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