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[/] [openmsp430/] [trunk/] [core/] - Rev 208

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Rev	Log message	Author	Age	Path
207	Simulation now works seamlessly under Linux, OS-X and Windows (Cygwin)	olivier.girard	3152d 19h	/openmsp430/trunk/core/
205	Thanks again to Johan W. good feedback, the following updates are implemented: - Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment. - Update oscillators enable generation to relax a critical timing paths in the ASIC version. - Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).	olivier.girard	3249d 19h	/openmsp430/trunk/core/
204	Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that).	olivier.girard	3256d 20h	/openmsp430/trunk/core/
202	Add DMA interface support + LINT cleanup	olivier.girard	3263d 19h	/openmsp430/trunk/core/
200	Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains.	olivier.girard	3424d 18h	/openmsp430/trunk/core/
192	Number of supported IRQs is now configurable to 14 (default), 30 or 62.	olivier.girard	3824d 20h	/openmsp430/trunk/core/
190	Remove dummy memory read access for CMP and BIT instructions.	olivier.girard	3964d 20h	/openmsp430/trunk/core/
188	Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c.	olivier.girard	3976d 20h	/openmsp430/trunk/core/
186	Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247	olivier.girard	4077d 20h	/openmsp430/trunk/core/
180	Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme. Thanks to Sebastien Van Cauwenberghe's contribution :-)	olivier.girard	4119d 19h	/openmsp430/trunk/core/
178	Update all linker scripts with a simplified version. Thanks to Mihai M. for this one :-)	olivier.girard	4128d 19h	/openmsp430/trunk/core/
175	Update hardware breakpoint unit with the followings: - fixed hardware breakpoint bug with CALL instructions. - modified data read watchpoint behavior to also trigger with read/modify/write instructions. - removed unused ports.	olivier.girard	4145d 19h	/openmsp430/trunk/core/
174	Cleanup dmem_wr generation logic. Important note: this is not a bug fix, only beautification.	olivier.girard	4145d 19h	/openmsp430/trunk/core/
154	The serial debug interface now supports the I2C protocol (in addition to the UART)	olivier.girard	4252d 20h	/openmsp430/trunk/core/
151	Add possibility to configure custom Program, Data and Peripheral memory sizes.	olivier.girard	4337d 18h	/openmsp430/trunk/core/
149	Update simulation regression result parser. Fixed failing SFR test (due to newer MSPGCC version). Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)	olivier.girard	4340d 20h	/openmsp430/trunk/core/
145	Add Dhrystone and CoreMark benchmarks to the simulation environment.	olivier.girard	4390d 19h	/openmsp430/trunk/core/
142	Beautify the linker script examples.	olivier.girard	4411d 20h	/openmsp430/trunk/core/
141	Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later)	olivier.girard	4415d 19h	/openmsp430/trunk/core/
139	Add some SVN ignore patterns	olivier.girard	4428d 05h	/openmsp430/trunk/core/

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] - Rev 208

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