| Rev |
Log message |
Author |
Age |
Path |
| 204 |
Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). |
olivier.girard |
3259d 10h |
/openmsp430/trunk/core/rtl/ |
| 202 |
Add DMA interface support + LINT cleanup |
olivier.girard |
3266d 09h |
/openmsp430/trunk/core/rtl/ |
| 200 |
Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. |
olivier.girard |
3427d 09h |
/openmsp430/trunk/core/rtl/ |
| 192 |
Number of supported IRQs is now configurable to 14 (default), 30 or 62. |
olivier.girard |
3827d 10h |
/openmsp430/trunk/core/rtl/ |
| 190 |
Remove dummy memory read access for CMP and BIT instructions. |
olivier.girard |
3967d 10h |
/openmsp430/trunk/core/rtl/ |
| 188 |
Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. |
olivier.girard |
3979d 10h |
/openmsp430/trunk/core/rtl/ |
| 186 |
Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 |
olivier.girard |
4080d 11h |
/openmsp430/trunk/core/rtl/ |
| 180 |
Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-) |
olivier.girard |
4122d 09h |
/openmsp430/trunk/core/rtl/ |
| 175 |
Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports. |
olivier.girard |
4148d 09h |
/openmsp430/trunk/core/rtl/ |
| 174 |
Cleanup dmem_wr generation logic. Important note: this is not a bug fix, only beautification. |
olivier.girard |
4148d 09h |
/openmsp430/trunk/core/rtl/ |
| 154 |
The serial debug interface now supports the I2C protocol (in addition to the UART) |
olivier.girard |
4255d 10h |
/openmsp430/trunk/core/rtl/ |
| 151 |
Add possibility to configure custom Program, Data and Peripheral memory sizes. |
olivier.girard |
4340d 08h |
/openmsp430/trunk/core/rtl/ |
| 149 |
Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface) |
olivier.girard |
4343d 10h |
/openmsp430/trunk/core/rtl/ |
| 134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4462d 10h |
/openmsp430/trunk/core/rtl/ |
| 132 |
Update FPGA examples with the POP.B bug fix |
olivier.girard |
4475d 10h |
/openmsp430/trunk/core/rtl/ |
| 130 |
Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) |
olivier.girard |
4483d 09h |
/openmsp430/trunk/core/rtl/ |
| 128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4559d 10h |
/openmsp430/trunk/core/rtl/ |
| 117 |
To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. |
olivier.girard |
4735d 11h |
/openmsp430/trunk/core/rtl/ |
| 112 |
Modified comment. |
olivier.girard |
4768d 10h |
/openmsp430/trunk/core/rtl/ |
| 111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4769d 10h |
/openmsp430/trunk/core/rtl/ |
