| Rev |
Log message |
Author |
Age |
Path |
| 200 |
Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. |
olivier.girard |
3421d 22h |
/openmsp430/trunk/core/rtl/verilog/ |
| 192 |
Number of supported IRQs is now configurable to 14 (default), 30 or 62. |
olivier.girard |
3822d 00h |
/openmsp430/trunk/core/rtl/verilog/ |
| 190 |
Remove dummy memory read access for CMP and BIT instructions. |
olivier.girard |
3962d 00h |
/openmsp430/trunk/core/rtl/verilog/ |
| 188 |
Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. |
olivier.girard |
3974d 00h |
/openmsp430/trunk/core/rtl/verilog/ |
| 186 |
Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 |
olivier.girard |
4075d 00h |
/openmsp430/trunk/core/rtl/verilog/ |
| 180 |
Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-) |
olivier.girard |
4116d 23h |
/openmsp430/trunk/core/rtl/verilog/ |
| 175 |
Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports. |
olivier.girard |
4142d 23h |
/openmsp430/trunk/core/rtl/verilog/ |
| 174 |
Cleanup dmem_wr generation logic. Important note: this is not a bug fix, only beautification. |
olivier.girard |
4142d 23h |
/openmsp430/trunk/core/rtl/verilog/ |
| 154 |
The serial debug interface now supports the I2C protocol (in addition to the UART) |
olivier.girard |
4250d 00h |
/openmsp430/trunk/core/rtl/verilog/ |
| 151 |
Add possibility to configure custom Program, Data and Peripheral memory sizes. |
olivier.girard |
4334d 22h |
/openmsp430/trunk/core/rtl/verilog/ |
| 149 |
Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface) |
olivier.girard |
4338d 00h |
/openmsp430/trunk/core/rtl/verilog/ |
| 134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4457d 00h |
/openmsp430/trunk/core/rtl/verilog/ |
| 132 |
Update FPGA examples with the POP.B bug fix |
olivier.girard |
4470d 00h |
/openmsp430/trunk/core/rtl/verilog/ |
| 130 |
Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) |
olivier.girard |
4477d 23h |
/openmsp430/trunk/core/rtl/verilog/ |
| 128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4553d 23h |
/openmsp430/trunk/core/rtl/verilog/ |
| 117 |
To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. |
olivier.girard |
4730d 01h |
/openmsp430/trunk/core/rtl/verilog/ |
| 112 |
Modified comment. |
olivier.girard |
4763d 00h |
/openmsp430/trunk/core/rtl/verilog/ |
| 111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4764d 00h |
/openmsp430/trunk/core/rtl/verilog/ |
| 106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4819d 22h |
/openmsp430/trunk/core/rtl/verilog/ |
| 105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
4834d 23h |
/openmsp430/trunk/core/rtl/verilog/ |
