| Rev |
Log message |
Author |
Age |
Path |
| 204 |
Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). |
olivier.girard |
3272d 22h |
/openmsp430/trunk/core/sim/ |
| 202 |
Add DMA interface support + LINT cleanup |
olivier.girard |
3279d 22h |
/openmsp430/trunk/core/sim/ |
| 200 |
Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. |
olivier.girard |
3440d 21h |
/openmsp430/trunk/core/sim/ |
| 192 |
Number of supported IRQs is now configurable to 14 (default), 30 or 62. |
olivier.girard |
3840d 23h |
/openmsp430/trunk/core/sim/ |
| 186 |
Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 |
olivier.girard |
4093d 23h |
/openmsp430/trunk/core/sim/ |
| 180 |
Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-) |
olivier.girard |
4135d 22h |
/openmsp430/trunk/core/sim/ |
| 178 |
Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-) |
olivier.girard |
4144d 21h |
/openmsp430/trunk/core/sim/ |
| 175 |
Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports. |
olivier.girard |
4161d 22h |
/openmsp430/trunk/core/sim/ |
| 154 |
The serial debug interface now supports the I2C protocol (in addition to the UART) |
olivier.girard |
4268d 22h |
/openmsp430/trunk/core/sim/ |
| 151 |
Add possibility to configure custom Program, Data and Peripheral memory sizes. |
olivier.girard |
4353d 21h |
/openmsp430/trunk/core/sim/ |
| 149 |
Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface) |
olivier.girard |
4356d 23h |
/openmsp430/trunk/core/sim/ |
| 145 |
Add Dhrystone and CoreMark benchmarks to the simulation environment. |
olivier.girard |
4406d 22h |
/openmsp430/trunk/core/sim/ |
| 142 |
Beautify the linker script examples. |
olivier.girard |
4427d 23h |
/openmsp430/trunk/core/sim/ |
| 141 |
Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) |
olivier.girard |
4431d 22h |
/openmsp430/trunk/core/sim/ |
| 138 |
Update simulation scripts to support Cygwin out of the box for Windows users. |
olivier.girard |
4444d 08h |
/openmsp430/trunk/core/sim/ |
| 134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4475d 22h |
/openmsp430/trunk/core/sim/ |
| 128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4572d 22h |
/openmsp430/trunk/core/sim/ |
| 122 |
Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator. |
olivier.girard |
4644d 22h |
/openmsp430/trunk/core/sim/ |
| 115 |
Add linker script example. |
olivier.girard |
4773d 23h |
/openmsp430/trunk/core/sim/ |
| 111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4782d 22h |
/openmsp430/trunk/core/sim/ |
