| Rev |
Log message |
Author |
Age |
Path |
| 204 |
Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). |
olivier.girard |
3257d 01h |
/openmsp430/trunk/core/sim/ |
| 202 |
Add DMA interface support + LINT cleanup |
olivier.girard |
3264d 00h |
/openmsp430/trunk/core/sim/ |
| 200 |
Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. |
olivier.girard |
3425d 00h |
/openmsp430/trunk/core/sim/ |
| 192 |
Number of supported IRQs is now configurable to 14 (default), 30 or 62. |
olivier.girard |
3825d 01h |
/openmsp430/trunk/core/sim/ |
| 186 |
Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 |
olivier.girard |
4078d 02h |
/openmsp430/trunk/core/sim/ |
| 180 |
Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-) |
olivier.girard |
4120d 00h |
/openmsp430/trunk/core/sim/ |
| 178 |
Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-) |
olivier.girard |
4129d 00h |
/openmsp430/trunk/core/sim/ |
| 175 |
Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports. |
olivier.girard |
4146d 00h |
/openmsp430/trunk/core/sim/ |
| 154 |
The serial debug interface now supports the I2C protocol (in addition to the UART) |
olivier.girard |
4253d 01h |
/openmsp430/trunk/core/sim/ |
| 151 |
Add possibility to configure custom Program, Data and Peripheral memory sizes. |
olivier.girard |
4337d 23h |
/openmsp430/trunk/core/sim/ |
| 149 |
Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface) |
olivier.girard |
4341d 01h |
/openmsp430/trunk/core/sim/ |
| 145 |
Add Dhrystone and CoreMark benchmarks to the simulation environment. |
olivier.girard |
4391d 01h |
/openmsp430/trunk/core/sim/ |
| 142 |
Beautify the linker script examples. |
olivier.girard |
4412d 01h |
/openmsp430/trunk/core/sim/ |
| 141 |
Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) |
olivier.girard |
4416d 00h |
/openmsp430/trunk/core/sim/ |
| 138 |
Update simulation scripts to support Cygwin out of the box for Windows users. |
olivier.girard |
4428d 10h |
/openmsp430/trunk/core/sim/ |
| 134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4460d 01h |
/openmsp430/trunk/core/sim/ |
| 128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4557d 01h |
/openmsp430/trunk/core/sim/ |
| 122 |
Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator. |
olivier.girard |
4629d 01h |
/openmsp430/trunk/core/sim/ |
| 115 |
Add linker script example. |
olivier.girard |
4758d 02h |
/openmsp430/trunk/core/sim/ |
| 111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4767d 01h |
/openmsp430/trunk/core/sim/ |
