| Rev |
Log message |
Author |
Age |
Path |
| 200 |
Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. |
olivier.girard |
3504d 04h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 192 |
Number of supported IRQs is now configurable to 14 (default), 30 or 62. |
olivier.girard |
3904d 06h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 186 |
Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 |
olivier.girard |
4157d 06h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 180 |
Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-) |
olivier.girard |
4199d 05h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 178 |
Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-) |
olivier.girard |
4208d 05h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 175 |
Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports. |
olivier.girard |
4225d 05h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 154 |
The serial debug interface now supports the I2C protocol (in addition to the UART) |
olivier.girard |
4332d 06h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 151 |
Add possibility to configure custom Program, Data and Peripheral memory sizes. |
olivier.girard |
4417d 04h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 149 |
Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface) |
olivier.girard |
4420d 06h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 145 |
Add Dhrystone and CoreMark benchmarks to the simulation environment. |
olivier.girard |
4470d 05h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 142 |
Beautify the linker script examples. |
olivier.girard |
4491d 06h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 141 |
Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) |
olivier.girard |
4495d 05h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4539d 06h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4636d 05h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 115 |
Add linker script example. |
olivier.girard |
4837d 07h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4846d 06h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4902d 04h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
4917d 05h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4922d 12h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
| 102 |
Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:
- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+ |
olivier.girard |
4923d 04h |
/openmsp430/trunk/core/sim/rtl_sim/src/ |
