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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] - Rev 202

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202 Add DMA interface support + LINT cleanup olivier.girard 3308d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3469d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
193 Update FPGA projects with latest core RTL changes. olivier.girard 3869d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 4009d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 4021d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4122d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
181 Update with latest oMSP Core version. olivier.girard 4164d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
178 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4173d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4190d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4297d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4382d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4385d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4456d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4473d 01h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
136 Update all FPGA projects with the latest core version. olivier.girard 4504d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4517d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4601d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
112 Modified comment. olivier.girard 4810d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4811d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4867d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/

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