OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] - Rev 213

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
212 Update all FPGA project examples to support both MSPGCC and TI/RedHat GCC toolchains. olivier.girard 3179d 23h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).		 olivier.girard 3304d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
204 Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). olivier.girard 3311d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
202 Add DMA interface support + LINT cleanup olivier.girard 3318d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3479d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
193 Update FPGA projects with latest core RTL changes. olivier.girard 3879d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 4019d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 4031d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4132d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
181 Update with latest oMSP Core version. olivier.girard 4174d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
178 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4183d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4200d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4307d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4392d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4395d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4466d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4482d 23h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
136 Update all FPGA projects with the latest core version. olivier.girard 4514d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4527d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4611d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.