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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] - Rev 186

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186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4096d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
181 Update with latest oMSP Core version. olivier.girard 4138d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4164d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4271d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4356d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4359d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
136 Update all FPGA projects with the latest core version. olivier.girard 4478d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4491d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4575d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
112 Modified comment. olivier.girard 4784d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4785d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4841d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4856d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4860d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4874d 19h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4897d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
85 Diverse RTL cosmetic updates. olivier.girard 4897d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4902d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
82 Update Actel example project:
- synthesis scripts.
- Spacewar demo program.
- SVN ignore patterns for diverse directories		 olivier.girard 4948d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
81 Initial synthesis, P&R setup for the Actel example project. olivier.girard 4951d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/

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