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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] - Rev 191

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Rev	Log message	Author	Age	Path
190	Remove dummy memory read access for CMP and BIT instructions.	olivier.girard	3986d 10h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
188	Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c.	olivier.girard	3998d 10h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
186	Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247	olivier.girard	4099d 10h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
181	Update with latest oMSP Core version.	olivier.girard	4141d 09h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
176	Update FPGA projects with latest openMSP430 core RTL	olivier.girard	4167d 09h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
155	Update FPGA projects with the latest openMSP430 verilog code.	olivier.girard	4274d 09h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
151	Add possibility to configure custom Program, Data and Peripheral memory sizes.	olivier.girard	4359d 08h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
149	Update simulation regression result parser. Fixed failing SFR test (due to newer MSPGCC version). Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)	olivier.girard	4362d 10h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
136	Update all FPGA projects with the latest core version.	olivier.girard	4481d 09h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
132	Update FPGA examples with the POP.B bug fix	olivier.girard	4494d 09h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
128	Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 )	olivier.girard	4578d 09h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
112	Modified comment.	olivier.girard	4787d 10h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4788d 10h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4844d 08h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	4859d 09h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4863d 10h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4877d 11h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	4900d 07h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
85	Diverse RTL cosmetic updates.	olivier.girard	4900d 09h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	4905d 10h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/

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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] - Rev 191

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