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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] - Rev 193

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Rev Log message Author Age Path
193 Update FPGA projects with latest core RTL changes. olivier.girard 3858d 23h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3998d 23h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 4010d 23h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4111d 23h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
181 Update with latest oMSP Core version. olivier.girard 4153d 22h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4179d 22h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4286d 22h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4371d 21h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4374d 23h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
136 Update all FPGA projects with the latest core version. olivier.girard 4493d 22h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4506d 22h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4590d 22h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
112 Modified comment. olivier.girard 4799d 22h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4800d 22h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4856d 20h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4871d 22h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4875d 23h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4889d 23h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4912d 20h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
85 Diverse RTL cosmetic updates. olivier.girard 4912d 22h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/

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