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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] - Rev 199

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Rev Log message Author Age Path
197 Fixed bug on the write strobe of the baudrate hi configuration register. olivier.girard 3902d 00h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
193 Update FPGA projects with latest core RTL changes. olivier.girard 3945d 00h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 4085d 00h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 4097d 00h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4198d 00h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
181 Update with latest oMSP Core version. olivier.girard 4239d 23h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4265d 23h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
171 Update in order to add Hardware breakpoint support.
Hardware breakpoint are here only added for development purpose in order to add multi-core features as well as software & hardware breakpoint support to the GDB-Proxy.		 olivier.girard 4299d 21h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
168 Add missing second oMSP system. olivier.girard 4320d 23h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
167 Update LX9 Microboard FPGA example.
It now includes a dual-core oMSP system with a shared 16kB program memory.
Each core has its own 2kB data memory and an additional 2kB shared data memory.		 olivier.girard 4320d 23h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
157 Re-create new LX9 Microboard project to show off the new I2C serial debug interface (and more to come).... olivier.girard 4372d 23h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/

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