OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] - Rev 202

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
202 Add DMA interface support + LINT cleanup olivier.girard 3266d 18h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3427d 17h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
197 Fixed bug on the write strobe of the baudrate hi configuration register. olivier.girard 3784d 19h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
193 Update FPGA projects with latest core RTL changes. olivier.girard 3827d 19h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3967d 19h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 3979d 19h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4080d 19h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
181 Update with latest oMSP Core version. olivier.girard 4122d 18h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4148d 18h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
171 Update in order to add Hardware breakpoint support.
Hardware breakpoint are here only added for development purpose in order to add multi-core features as well as software & hardware breakpoint support to the GDB-Proxy.		 olivier.girard 4182d 16h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
168 Add missing second oMSP system. olivier.girard 4203d 18h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
167 Update LX9 Microboard FPGA example.
It now includes a dual-core oMSP system with a shared 16kB program memory.
Each core has its own 2kB data memory and an additional 2kB shared data memory.		 olivier.girard 4203d 18h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
157 Re-create new LX9 Microboard project to show off the new I2C serial debug interface (and more to come).... olivier.girard 4255d 18h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.