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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] - Rev 213

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212 Update all FPGA project examples to support both MSPGCC and TI/RedHat GCC toolchains. olivier.girard 3286d 17h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).		 olivier.girard 3411d 07h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
204 Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). olivier.girard 3418d 07h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
202 Add DMA interface support + LINT cleanup olivier.girard 3425d 06h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3586d 06h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
197 Fixed bug on the write strobe of the baudrate hi configuration register. olivier.girard 3943d 07h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
193 Update FPGA projects with latest core RTL changes. olivier.girard 3986d 07h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 4126d 07h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 4138d 07h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4239d 08h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
181 Update with latest oMSP Core version. olivier.girard 4281d 06h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4307d 06h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
171 Update in order to add Hardware breakpoint support.
Hardware breakpoint are here only added for development purpose in order to add multi-core features as well as software & hardware breakpoint support to the GDB-Proxy.		 olivier.girard 4341d 05h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
168 Add missing second oMSP system. olivier.girard 4362d 06h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
167 Update LX9 Microboard FPGA example.
It now includes a dual-core oMSP system with a shared 16kB program memory.
Each core has its own 2kB data memory and an additional 2kB shared data memory.		 olivier.girard 4362d 07h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
157 Re-create new LX9 Microboard project to show off the new I2C serial debug interface (and more to come).... olivier.girard 4414d 06h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/

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