OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] - Rev 221

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
212 Update all FPGA project examples to support both MSPGCC and TI/RedHat GCC toolchains. olivier.girard 3159d 06h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).		 olivier.girard 3283d 20h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
204 Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). olivier.girard 3290d 20h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
202 Add DMA interface support + LINT cleanup olivier.girard 3297d 20h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3458d 19h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
197 Fixed bug on the write strobe of the baudrate hi configuration register. olivier.girard 3815d 20h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
193 Update FPGA projects with latest core RTL changes. olivier.girard 3858d 20h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3998d 20h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 4010d 20h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4111d 21h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
181 Update with latest oMSP Core version. olivier.girard 4153d 19h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4179d 19h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
171 Update in order to add Hardware breakpoint support.
Hardware breakpoint are here only added for development purpose in order to add multi-core features as well as software & hardware breakpoint support to the GDB-Proxy.		 olivier.girard 4213d 18h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
168 Add missing second oMSP system. olivier.girard 4234d 20h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
167 Update LX9 Microboard FPGA example.
It now includes a dual-core oMSP system with a shared 16kB program memory.
Each core has its own 2kB data memory and an additional 2kB shared data memory.		 olivier.girard 4234d 20h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/
157 Re-create new LX9 Microboard project to show off the new I2C serial debug interface (and more to come).... olivier.girard 4286d 19h /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.