OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] - Rev 212

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
212 Update all FPGA project examples to support both MSPGCC and TI/RedHat GCC toolchains. olivier.girard 3119d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).		 olivier.girard 3244d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
204 Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). olivier.girard 3251d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
202 Add DMA interface support + LINT cleanup olivier.girard 3258d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3419d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
197 Fixed bug on the write strobe of the baudrate hi configuration register. olivier.girard 3776d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
193 Update FPGA projects with latest core RTL changes. olivier.girard 3819d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3959d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 3971d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4072d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
181 Update with latest oMSP Core version. olivier.girard 4114d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
179 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4123d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4140d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4247d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
153 Update XFLOW scripts to bring more automation.
Several bitstreams are now checked in for direct use.		 olivier.girard 4302d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4332d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4335d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4406d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4422d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
136 Update all FPGA projects with the latest core version. olivier.girard 4454d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.