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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] - Rev 202

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Rev Log message Author Age Path
202 Add DMA interface support + LINT cleanup olivier.girard 3265d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3426d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
197 Fixed bug on the write strobe of the baudrate hi configuration register. olivier.girard 3783d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
193 Update FPGA projects with latest core RTL changes. olivier.girard 3826d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3966d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 3978d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4079d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
181 Update with latest oMSP Core version. olivier.girard 4121d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
179 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4130d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4147d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4254d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
153 Update XFLOW scripts to bring more automation.
Several bitstreams are now checked in for direct use.		 olivier.girard 4309d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4339d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4342d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4413d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4430d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
136 Update all FPGA projects with the latest core version. olivier.girard 4461d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4474d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4558d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
112 Modified comment. olivier.girard 4767d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/

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