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Rev Log message Author Age Path
195 Update HTML documentation with configurable number of IRQ option. olivier.girard 4336d 23h /
194 Update PDF and ODT documentation. olivier.girard 4337d 00h /
193 Update FPGA projects with latest core RTL changes. olivier.girard 4337d 00h /
192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 4337d 00h /
191 Update ChangeLog olivier.girard 4477d 00h /
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 4477d 00h /
189 Update ChangeLog olivier.girard 4489d 00h /
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 4489d 00h /
187 Update ChangeLog olivier.girard 4590d 00h /
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4590d 00h /
185 Update Altera FPGA example bitstream (no functional change... only generated with a newer Quartus version) olivier.girard 4591d 01h /
184 Fixed some project settings for newer Quartus version (12.1) olivier.girard 4591d 01h /
183 Update ChangeLog olivier.girard 4631d 23h /
182 Minor update to reflect new ASIC_CLOCKING option. olivier.girard 4631d 23h /
181 Update with latest oMSP Core version. olivier.girard 4631d 23h /
180 Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-)		 olivier.girard 4631d 23h /
179 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4640d 23h /
178 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4640d 23h /
177 Update ChangeLog olivier.girard 4657d 23h /
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4657d 23h /

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