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[/] [openmsp430/] [trunk/] [core/] - Rev 210

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207 Simulation now works seamlessly under Linux, OS-X and Windows (Cygwin) olivier.girard 3133d 21h /openmsp430/trunk/core/
205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).		 olivier.girard 3230d 21h /openmsp430/trunk/core/
204 Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). olivier.girard 3237d 21h /openmsp430/trunk/core/
202 Add DMA interface support + LINT cleanup olivier.girard 3244d 21h /openmsp430/trunk/core/
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3405d 20h /openmsp430/trunk/core/
192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 3805d 22h /openmsp430/trunk/core/
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3945d 21h /openmsp430/trunk/core/
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 3957d 21h /openmsp430/trunk/core/
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4058d 22h /openmsp430/trunk/core/
180 Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-)		 olivier.girard 4100d 20h /openmsp430/trunk/core/
178 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4109d 20h /openmsp430/trunk/core/
175 Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports.		 olivier.girard 4126d 20h /openmsp430/trunk/core/
174 Cleanup dmem_wr generation logic. Important note: this is not a bug fix, only beautification. olivier.girard 4126d 20h /openmsp430/trunk/core/
154 The serial debug interface now supports the I2C protocol (in addition to the UART) olivier.girard 4233d 21h /openmsp430/trunk/core/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4318d 19h /openmsp430/trunk/core/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4321d 21h /openmsp430/trunk/core/
145 Add Dhrystone and CoreMark benchmarks to the simulation environment. olivier.girard 4371d 21h /openmsp430/trunk/core/
142 Beautify the linker script examples. olivier.girard 4392d 21h /openmsp430/trunk/core/
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 4396d 20h /openmsp430/trunk/core/
139 Add some SVN ignore patterns olivier.girard 4409d 07h /openmsp430/trunk/core/

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