| Rev |
Log message |
Author |
Age |
Path |
| 211 |
Add custom printf function to reduce program memory footprint (the TI/RH GCC version is huge). Note that this function was created by DJ Delorie ( http://www.delorie.com/ ) |
olivier.girard |
3091d 14h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 207 |
Simulation now works seamlessly under Linux, OS-X and Windows (Cygwin) |
olivier.girard |
3119d 04h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 204 |
Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). |
olivier.girard |
3223d 04h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 202 |
Add DMA interface support + LINT cleanup |
olivier.girard |
3230d 04h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 200 |
Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. |
olivier.girard |
3391d 03h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 192 |
Number of supported IRQs is now configurable to 14 (default), 30 or 62. |
olivier.girard |
3791d 04h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 186 |
Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 |
olivier.girard |
4044d 05h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 180 |
Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-) |
olivier.girard |
4086d 03h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 178 |
Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-) |
olivier.girard |
4095d 03h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 175 |
Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports. |
olivier.girard |
4112d 03h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 154 |
The serial debug interface now supports the I2C protocol (in addition to the UART) |
olivier.girard |
4219d 04h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 151 |
Add possibility to configure custom Program, Data and Peripheral memory sizes. |
olivier.girard |
4304d 02h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 149 |
Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface) |
olivier.girard |
4307d 04h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 145 |
Add Dhrystone and CoreMark benchmarks to the simulation environment. |
olivier.girard |
4357d 04h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 142 |
Beautify the linker script examples. |
olivier.girard |
4378d 04h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 141 |
Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) |
olivier.girard |
4382d 03h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 138 |
Update simulation scripts to support Cygwin out of the box for Windows users. |
olivier.girard |
4394d 14h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4426d 04h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4523d 04h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 122 |
Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator. |
olivier.girard |
4595d 04h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 115 |
Add linker script example. |
olivier.girard |
4724d 05h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4733d 04h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4789d 03h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
4804d 04h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4809d 10h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 102 |
Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:
- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+ |
olivier.girard |
4810d 03h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 101 |
Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. |
olivier.girard |
4810d 04h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 99 |
Small fix for CVER simulator support. |
olivier.girard |
4814d 04h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 98 |
Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated. |
olivier.girard |
4814d 04h |
/openmsp430/trunk/core/sim/rtl_sim/ |
| 95 |
Update some test patterns for the additional simulator supports. |
olivier.girard |
4818d 04h |
/openmsp430/trunk/core/sim/rtl_sim/ |
