URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [mpy_basic.v] - Rev 202

Rev	Log message	Author	Age	Path
202	Add DMA interface support + LINT cleanup	olivier.girard	3231d 20h	/openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v
186	Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247	olivier.girard	4045d 22h	/openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4734d 21h	/openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v
67	Added 16x16 Hardware Multiplier.	olivier.girard	5174d 06h	/openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v