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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_multiplier.v] - Rev 202

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202 Add DMA interface support + LINT cleanup olivier.girard 3232d 01h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 4046d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v
136 Update all FPGA projects with the latest core version. olivier.girard 4428d 01h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4735d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4789d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4810d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5174d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v

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