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pipeline #40
Closed clould365 opened this issue over 11 years ago
clould365 commented over 11 years ago

In the overview page, you describe an add instruction. Stage#0 1 2 3 4. I think this is the datapath of an add instruction, right?

Are the word "stage" in "two stage pipeline" and "Stage#0 1 2 3 4" the same meaning?

rhoads was assigned over 11 years ago
rhoads commented over 11 years ago

Yes, the datapath of an add instruction is explained.

Yes, I mean for "stage" to have the same meaning.

I'm not sure that stage 0 really counts as a separate stage so stage #1 and stage #2 are really the two stage pipeline. If there is a read or a write there needs to be extra stage while using the address and data buses. Using pipeline.vhd can also add an additional pipeline stage.

clould365 commented over 11 years ago

In the textbooks I have read, they all divided stages using a clock controlling registers, just like: https://docs.google.com/file/d/0B1UAdqPpmnNROEgzTkJ1MFpPR0E/edit

So, 1. Why "the memory returns the opcode" is the end of stage 1? I don't think there are registers between control.vhd and mem_control.vhd holding the opcode, are there?

  1. If we use your two stages pipeline, there are sigD in your mlite_cpu. I think these are registers, so there is a stage boundary here. But why you don't count here as a stage boundary? If sigD are not the stage boundary, what's their function? Ca n we remove them if we use two stage pipeline?

I guess there must be misunderstandings about pipeline in my mind....

rhoads commented over 11 years ago

Answers:

  1. In mem_ctrl.vhd line 176, the opcode_reg is loaded at the end of stage 1.

  2. In mlite_cpu.vhd line 296, if pipeline_stages is 2 then all of the sigD signals are equal to the sig signals without any delay. There isn't a "if rising_edge(clk)" condition that would turn the signals into a register. Only if the pipeline entity is enabled are the sigD signals delayed by a clock.

rhoads closed this over 11 years ago

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