Created: Sep 25, 2001
Updated: Nov 21, 2016
SVN Updated: Aug 30, 2014
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The Plasma CPU is a small synthesizable 32-bit RISC microprocessor. It is currently running a live web server with an interrupt controller, UART, SRAM or DDR SDRAM controller, and Ethernet controller. The Plasma CPU executes all MIPS I(TM) user mode instructions except unaligned load and store operations (see "Avoiding Limitations" below).
This "clean room" CPU core is implemented in VHDL with either a two or three-stage pipeline. It is running at 25 MHz on a Xilinx FPGA and also verified on an Altera FPGA.
The Plasma CPU along with the Plasma RTOS and TCP/IP protocol stack are now running a live Web Server
on a Xilinx FPGA.
The CPU is implemented with a two or three stage pipeline with an additional optional stage for memory read and writes. (Using the three stage pipeline enables "pipeline.vhd" which delays some control signals into the next stage.)
An ADD instruction would take the following steps:
1. The "pc_next" entity passes the program counter (PC) to the "mem_ctrl" entity which fetches the opcode from memory.
2. The memory returns the opcode.
3. "Mem_ctrl" passes the opcode to the "control" entity.
4. "Control" converts the 32-bit opcode to a 60-bit VLWI opcode and sends control signals to the other entities.
5. Based on the rs_index and rt_index control signals, "reg_bank" sends the 32-bit reg_source and reg_target to "bus_mux".
Stage #3 (part of stage #2 if using two stage pipeline):
6. Based on the a_source and b_source control signals, "bus_mux" multiplexes reg_source onto a_bus and reg_target onto b_bus.
7. Based on the alu_func control signals, "alu" adds the values from a_bus and b_bus and places the result on c_bus.
8. Based on the c_source control signals, "bus_mux" multiplexes c_bus onto reg_dest.
9. Based on the rd_index control signal, "reg_bank" saves reg_dest into the correct register.
Stage #4 (part of stage #3 if using two stage pipeline):
10. Read or write memory if needed.
Plasma Version 3 Features
The Plasma Version 3 core now contains a bidirectional serial port, interrupt controller, and hardware timer. Version 3.5 added a DDR SDRAM controller, Ethernet MAC, and Flash interface. There is C and assembly code for the Plasma Real-Time Operating System -- a fully preemptive RTOS supporting threads, semaphores, mutexes, message queues, timers, heaps, an interrupt manager, ANSI C library, single precision floating point library, TCP/IP protocol stack, and Web server.
The Opencores Subversion web page can create the 130KB plasma_latest.tar.gz
file containing all the latest code.
See the tabs at the top for additional build instructions:
- The Plasma CPU instruction set
- Building the tools
- Additional Linux GNU MIPS tools
- Building the Plasma RTOS
- Building the Plasma TCP/IP stack
The implementation is based on information found in:
- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
- "The Designer's Guide to VHDL" by Peter J. Ashenden
The MIPS I(TM) instruction set can be found by:
- Go to the MIPS Technologies, Inc. Web site http://www.mips.com/.
- Under the Products menu, click on Resource Library.
- Click on Product Materials in the submenu on the left.
- Click on MIPS Architecture from the next menu on the left.
- Finally, click on the link for "MIPS32® Architecture for Programmers Volume II: The MIPS32® Instruction Set (.pdf)".
The CPU core operates in Big Endian mode by default. To operate in Little Endian mode, change "little_endian" from "00" to "11" in the file mem_ctrl.vhd.
All signals are active high. Here are the signals for writing a character to address 0xffff when using a two stage pipeline:
entity mlite_cpu is
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end; --entity mlite_cpu
addr value opcode
3c: 00000000 nop
40: 34040041 li $a0,0x41
44: 3405ffff li $a1,0xffff
48: a0a40000 sb $a0,0($a1)
4c: 00000000 nop
50: 00000000 nop
reset_in byte_we Stages
ns address data_w data_r 40 44 48 4c 50
3600 0 0 00000040 00000000 34040041 0 0 1
3700 0 0 00000044 00000000 3405FFFF 0 0 2 1
3800 0 0 00000048 00000000 A0A40000 0 0 2 1
3900 0 0 0000004C 41414141 00000000 0 0 2 1
4000 0 0 0000FFFC 41414141 XXXXXX41 1 0 3 2
4100 0 0 00000050 00000000 00000000 0 0 1
The CPU core was synthesized for several different FPGAs:
- Xilinx Spartan-3E Starter Kit Board with a XC3S500 used 2021 of 4656 slices (43 percent). Image includes DDR and Ethernet controllers.
- Removing the multiplication unit reduces the size by 558 slices.
- Xilinx Spartan-3 Starter Kit Board with an Xilinx XC3S200 Spartan-3 FPGA.
- Altera EP20K200EFC484-2X FPGA.
- All MIPS I(TM) instructions are implemented and tested (except the unsupported previously patented unaligned load and store opcodes).
- Currently running on an Altera EP20K200EFC484-2X FPGA and a Xilinx XC3S500 and XC3S200 FPGA.
- Also running on a Xilinx Spartan-3E starter kit with DDR SDRAM, Ethernet MAC, and Flash Controller.
- Running at 50 MHz on newer Xilinx FPGAs with three stage pipeline.
- See "opcodes.asm" for regression test.
- Supports Interrupts.
- Includes several C test programs: Calculating PI; Prime Numbers; Showing Numbers Using Words; the Plasma RTOS; and single precision floating point library.
MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of MIPS Technologies, Inc. in the United States and other countries. MIPS Technologies, Inc. does not endorse and is not associated with this project. OpenCores and Steve Rhoads are not affiliated in any way with MIPS Technologies, Inc.
The Plasma CPU project has been placed into the public domain by its original author and is free for commercial and non-commercial use.
This software is provided "as is" and any express or implied warranties, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose are disclaimed.
This section describes how to avoid the two main limitations of the Plasma CPU core. The first limitation is that unaligned load and store operations are not supported since they were patented. This means that when loading or storing 32-bit values the memory address must be on a 32-bit aligned address. [The patent
for the unaligned memory access instructions expired Dec 23, 2006.]
Most RISC CPUs have limited support for unaligned memory accesses. The GCC MIPS compiler does not normally generate unaligned memory accesses. Try compiling a C program and then look in the listing file if any of these MIPS instructions are used: LWL, LWR, SWL, or SWR. If needed, there is a GCC patch to never generate unaligned memory accesses at ultra-embedded
The second main limitation of the Plasma CPU is that exceptions (BREAK and SYSCALL opcodes) must not be placed immediately after a branch instruction (in the branch delay slot). The main uses for exceptions are software interrupts for debugger support and calling operating system calls.
Plasma CPU Web Articles
Several groups have published how they have used the Plasma CPU.