The Plasma CPU is a small synthesizable 32-bit RISC microprocessor. It is currently running a live web server with an interrupt controller, UART, SRAM or DDR SDRAM controller, and Ethernet controller. The Plasma CPU executes all MIPS I(TM) user mode instructions except unaligned load and store operations (see "Avoiding Limitations" below).
This "clean room" CPU core is implemented in VHDL with either a two or three-stage pipeline. It is running at 25 MHz on a Xilinx FPGA and also verified on an Altera FPGA.
The Plasma CPU along with the Plasma RTOS and TCP/IP protocol stack are now running a live Web Server on a Xilinx FPGA.
The CPU is implemented with a two or three stage pipeline with an additional optional stage for memory read and writes. (Using the three stage pipeline enables "pipeline.vhd" which delays some control signals into the next stage.)
An ADD instruction would take the following steps:
The Plasma Version 3 core now contains a bidirectional serial port, interrupt controller, and hardware timer. Version 3.5 added a DDR SDRAM controller, Ethernet MAC, and Flash interface. There is C and assembly code for the Plasma Real-Time Operating System -- a fully preemptive RTOS supporting threads, semaphores, mutexes, message queues, timers, heaps, an interrupt manager, ANSI C library, single precision floating point library, TCP/IP protocol stack, and Web server.
|FILE||PURPOSE (Directory: vhdl)|
|code.txt||Input opcodes for the test bench -- test.axf "converted"|
|mlite_pack.vhd||Constants and Functions Package|
|tbench.vhd||Test Bench that uses plasma.vhd|
|plasma_if.vhd||Top level interface to Xilinx or Altera FPGA|
|plasma_3e.vhd||Top level interface to Xilinx Spartan-3E with DDR|
|-plasma.vhd||CPU core with RAM and UART|
|--cache.vhd||Optional 4KB cache|
|--ram.vhd||Internal RAM for Altera FPGA|
|--ram_xilinx.vhd||Internal RAM for Xilinx FPGA|
|--uart.vhd||UART (can pause CPU if needed)|
|--eth_dma.vhd||Ethernet MAC with DMA|
|--mlite_cpu.vhd||Top Level VHDL for CPU core|
|---alu.vhd||Arithmetic Logic Unit|
|---bus_mux.vhd||BUS Multiplex Unit|
|---mult.vhd||Multiplication and Division Unit|
|---pc_next.vhd||Program Counter Unit|
|---reg_bank.vhd||Register Bank for 32, 32-bit Registers|
|FILE||PURPOSE (Directory: tools)|
|makefile||Makefile for the PC for creating "code.txt"|
|plasma.h||Plasma header file for register addresses|
|boot.asm||Initializes $gp and $sp, clears .bss|
|opcodes.asm||Tests all the MIPS I(tm) opcodes|
|convert.c||Converts test.axf to code.txt|
|ram_image.c||Creates Xilinx RAM file ram_image.vhd from ram_xilinx.vhd and code.txt|
|bootldr.c||Serial port boot loader that can download another program|
|etermip.c||Terminal program to download code and transfer Ethernet packets||mlite.c||Simulates the CPU in software|
|bintohex.c||Converts test.exe to code[0-3].hex for lpm_ram for Altera FPGA|
|test.c||Test program (opcodes) for the CPU core|
|pi.c||Calculates the first 16 digits of PI|
|count.c||Test program that counts using words|
|ddr_init.c||Initialize the DDR chip|
|FILE||PURPOSE (Directory: kernel)|
|makefile||Makefile for Plasma RTOS|
|rtos.h||Header file for Plasma RTOS|
|rtos.c||Plasma pre-emptive Real-Time Operating System|
|libc.c||ANSI C library subset|
|math.c||Single precision floating point library|
|uart.c||Serial port driver|
|rtos_test.c||Test the RTOS functions|
|tcpip.h||TCP/IP header file|
|tcpip.c||TCP/IP protocol stack|
|netutil.c||FTP server/client and telnet server|
The Opencores Subversion web page can create the 130KB plasma_latest.tar.gz file containing all the latest code.
The MIPS(tm) GCC ELF compiler for Windows is available gccmips_elf.zip (2.4MB). The OpenCores server wouldn't let me save zip files so I had to rename it with an '.odt' extention. Rename the file from gccmips_elf.odt to gccmips_elf.zip before unzipping the files into the trunk\gccmips_elf directory. Add this directory to your executable PATH environment: set path=%PATH%;YOUR_DIR\trunk\gccmips_elf
If you use Windows and don't have a Microsoft C compiler for Windows, you will need pre-compiled versions of the tools (rename as tools.zip) which should be placed in the tools directory.
You may also need a Windows version of gmake. Rename the file gmake_zip.odt to gmake.zip before unzipping.
See the tabs at the top for additional build instructions:
The CPU core operates in Big Endian mode by default. To operate in Little Endian mode, change "little_endian" from "00" to "11" in the file mem_ctrl.vhd.
All signals are active high. Here are the signals for writing a character to address 0xffff when using a two stage pipeline:
entity mlite_cpu is
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end; --entity mlite_cpu
addr value opcode
3c: 00000000 nop
40: 34040041 li $a0,0x41
44: 3405ffff li $a1,0xffff
48: a0a40000 sb $a0,0($a1)
4c: 00000000 nop
50: 00000000 nop
reset_in byte_we Stages
ns address data_w data_r 40 44 48 4c 50
3600 0 0 00000040 00000000 34040041 0 0 1
3700 0 0 00000044 00000000 3405FFFF 0 0 2 1
3800 0 0 00000048 00000000 A0A40000 0 0 2 1
3900 0 0 0000004C 41414141 00000000 0 0 2 1
4000 0 0 0000FFFC 41414141 XXXXXX41 1 0 3 2
4100 0 0 00000050 00000000 00000000 0 0 1
The CPU core was synthesized for several different FPGAs:
MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of MIPS Technologies, Inc. in the United States and other countries. MIPS Technologies, Inc. does not endorse and is not associated with this project. OpenCores and Steve Rhoads are not affiliated in any way with MIPS Technologies, Inc.
The Plasma CPU project has been placed into the public domain by its original author and is free for commercial and non-commercial use.
This software is provided "as is" and any express or implied warranties, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose are disclaimed.
This section describes how to avoid the two main limitations of the Plasma CPU core. The first limitation is that unaligned load and store operations are not supported since they were patented. This means that when loading or storing 32-bit values the memory address must be on a 32-bit aligned address. [The patent for the unaligned memory access instructions expired Dec 23, 2006.]
Most RISC CPUs have limited support for unaligned memory accesses. The GCC MIPS compiler does not normally generate unaligned memory accesses. Try compiling a C program and then look in the listing file if any of these MIPS instructions are used: LWL, LWR, SWL, or SWR. If needed, there is a GCC patch to never generate unaligned memory accesses at ultra-embedded->GCC Modifications.
The second main limitation of the Plasma CPU is that exceptions (BREAK and SYSCALL opcodes) must not be placed immediately after a branch instruction (in the branch delay slot). The main uses for exceptions are software interrupts for debugger support and calling operating system calls.
Several groups have published how they have used the Plasma CPU.