anyone pls help us to write vhdl code for i2c and spi protocol.. both master and slave with testbench.
thanks in advance

You should be able to find plenty of examples of what you need in the projects directory. Take a look at what others have done, and that should give you some ideas.

Will you be posting your work when you are done?

Dan

Hello,
We have a project on creating "VIP of I2C MASTER", we need a I2Cslave DUT, so , we have downloaded I2Cslave project from opencores...we are facing problem in understanding the DUT..Kindly help us out..

How should we implement the master VIP to test the I2Cslave?

The RTL code which we have referred to is attached below.. In that the reset, and clock, are understood , but we are not getting the use of rest of the 8 registers used in the portlist of I2Cslave DUT.

This confusion is due to the fact that according to the protocol, we have only 2 main and only connections to the slave..

Thanking you..

I'm not sure I understand your question. Here's some possible helps:

The I2C protocol is difficult to implement internally to an FPGA, since it depends upon pullup resistors that are available on output ports only.

However, once you have it set up right, two chips should communicate nicely over the I2C using only two wires--one controlled by the master only, the second wire jointly controlled by the master and the slave. These wires are the sda and scl lines in the i2cSlave file you posted. These are probably the two wires you are thinking of.

The other connections to the I2C slave (myReg0-myReg7) are, IIRC, connections to the rest of the slave device. According to the documentation, the device allows you to set and query up to 256 registers, although the register module appears to only support 8 output registers and 4 input registers.

Incidentally, for those others reading, the file appears to come from Steve Fielding's I2C Slave project.

Perhaps if you

Dan

Hello Dan,

Thank you for replying us..

We will be working on this...